1. Field of the Invention
The present invention relates to semiconductor devices, and in particular, relates to bonding between package pins and a chip.
2. Background Information
For electronic appliances in general, processing speeds keep further rising in order to meet demands for more functions and higher performances. In addition to that, further increases in speed are being required not only in communications between modules within an electronic appliance but also in communications between electronic appliances. Serial transmission has an advantage over parallel transmission in further increases in speed in communications. Accordingly, serial transmission schemes are now widely adopted by various standards, such as USB, IEEE1394, LVDS, DVI, HDMI, serial ATA, and PCI express. An increasing number of miniature electronic devices such as cellular phones, in particular, have adopted serial transmission schemes because of the advantage that a smaller number of signal lines are required.
Differential transmission schemes are usually adopted into serial transmission since its signal frequencies are extremely high, e.g. of the order of GHz, thereby reducing the influence of noises over signals and electromagnetic interference caused by signal transmissions. Impedance matching between signal lines and interfaces is required to be attained with further higher precision, in order to further improve transmission speeds of serial signals, in particular, in high frequency bands. Thus, reflections, distortions, and attenuation of signals at the interfaces should be further suppressed.
In conventional semiconductor devices, parasitic inductances and capacitances present in signal lines are reduced as much as possible, and thereby reflections, distortions, and attenuation of signals are suppressed. For example, inductances are mainly suppressed in conducting paths such as package pins and bonding wires, while capacitances of electrostatic discharge (ESD) protection circuits and input/output (I/O) circuits that are connected to bonding pads are mainly suppressed in a chip. However, it is difficult to attain the impedance matching between the signal lines and the I/O circuits with higher precision in the approach of only reducing the parasitic reactances (inductances/capacitances) of the signal lines. In addition, the reduction in capacitance prevents the ESD protection circuits from further improving reliability.
For example, the published PCT international application WO00051012 discloses a semiconductor device shown in FIG. 8, which is known as a conventional semiconductor device that can attain high-precision impedance matching between signal lines under the condition that high reliability of ESD protection circuits is maintained. An ESD protection circuit 107 and an I/O circuit 108 are connected to the same package pin 101 through different signal lines (sets of bonding pads 103, 104 and bonding wires 105, 106, respectively) in the semiconductor device 100. Furthermore, equivalent inductances L5 and L6 of the bonding wires 105 and 106 and the coupling coefficient k between them are adjusted, depending on the lengths of the bonding wires 105 and 106 and the angle between them. (See FIG. 9.) Thereby, the level vs of the signal that is received or sent by the I/O circuit 108 is maintained to be sufficiently high at up to a sufficiently high frequency band, while the capacitance C7 of the ESD protection circuit 107 is maintained to be sufficiently large.
For miniature electronic devices such as cellular phones, in particular, it is desirable to integrate a larger number and wider variety of modules into a single LSI in view of further miniaturization and power reduction. The number and variety of modules that can be integrated into a LSI of a fixed size are limited by the number of signal lines connectable to the LSI as well as the sizes of the modules. Accordingly, it is desirable that the largest possible number of signal lines are connectable to the LSI.
However, in the semiconductor device shown in FIG. 8, for example, the two bonding pads 103 and 104 to be connected to the same package pin 101 are arranged in parallel along an edge of the chip 102. Accordingly, the upper number limit of the package pins 101 connectable to the chip 102, that is, the upper number limit of the signal lines, is only half of the upper number limit of the bonding pads that can be arranged along the perimeter of the chip 102. Such a limitation on the number of signal lines is not desirable since it prevents increases in the number and variety of modules that can be integrated into the chip 102. Furthermore, the miniaturization of the chip 102 provides a finer pitch between the two bonding pads 103 and 104 arranged in parallel along an edge of the chips 102, and then, the difference in length and the angle between the bonding wires 105 and 106 can be adjusted within a narrower range. Accordingly, it is difficult to maintain the impedance matching between the I/O circuit 108 and the signal line 101-106-104 with sufficiently high precision under the condition that the capacitance of the ESD protection circuit 107 is maintained to be sufficiently large.
In view of the above, there exists a need for a semiconductor device which overcomes the above mentioned problems in the prior art. This invention addresses this need in the prior art as well as other needs, which will become apparent to those skilled in the art from this disclosure.